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N. Ruiz Amador
N. Ruiz Amador
STMicroelectronics
Electronic engineering
Top-down and bottom-up design
system level
System on a chip
Logic gate
2
Papers
28
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A predictive bottom-up hierarchical approach to digital system reliability
2012
IRPS | International Reliability Physics Symposium
V. Huard
E. Pion
F. Cacho
Damien Croain
V. Robert
R. Delater
P. Mergault
Sylvain Engels
Philippe Flatresse
N. Ruiz Amador
Lorena Anghel
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Citations (27)
Bottom-up digital system-level reliability modeling
2011
CICC | Custom Integrated Circuits Conference
N. Ruiz Amador
V. Huard
E. Pion
F. Cacho
Damien Croain
V. Robert
Sylvain Engels
Philippe Flatresse
Lorena Anghel
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Citations (1)
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