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P. Mergault
P. Mergault
STMicroelectronics
Ageing
Electronic engineering
System on a chip
Logic gate
Engineering
2
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35
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28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications
2016
VLSIC | Symposium on VLSI Circuits
R. Ranica
N. Planes
V. Huard
O. Weber
D. Noblet
Damien Croain
Fabien Giner
Sylvie Naudet
P. Mergault
S. Ibars
Alexandre Villaret
M. Parra
S. Haendler
M. Quoirin
F. Cacho
C. Julien
F. Terrier
Lorenzo Ciampolini
David Turgis
Christophe Lecocq
F. Arnaud
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Citations (8)
A predictive bottom-up hierarchical approach to digital system reliability
2012
IRPS | International Reliability Physics Symposium
V. Huard
E. Pion
F. Cacho
Damien Croain
V. Robert
R. Delater
P. Mergault
Sylvain Engels
Philippe Flatresse
N. Ruiz Amador
Lorena Anghel
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Citations (27)
1