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Fariborz Assaderaghi
Fariborz Assaderaghi
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Timing margin
S-LINK
Dynamic random-access memory
Computer science
Electronic engineering
3
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57
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A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
2009
IEEE Journal of Solid-state Circuits
Hae-Chang Lee
Kun-Yung Ken Chang
Jung-Hoon Chun
Ting Wu
Yohan Frans
Brian S. Leibowitz
Nhat Nguyen
T. J. Chin
Kambiz Kaviani
Jie Shen
Xudong Shi
Wendemagegnehu T. Beyene
Simon Li
Reza Navid
Marko Aleksic
Fred S. Lee
Fredy Quan
Jared L. Zerbe
Rich Perego
Fariborz Assaderaghi
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Citations (50)
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
2009
VLSIC | Symposium on VLSI Circuits
Hae-Chang Lee
Kun-Yung Ken Chang
Jung-Hoon Chun
Ting Wu
Yohan Frans
Brian S. Leibowitz
Nhat Nguyen
T. J. Chin
Kambiz Kaviani
Jie Shen
Xudong Shi
Wendemagegnehu T. Beyene
Simon Li
Reza Navid
Marko Aleksic
Fred S. Lee
Fredy Quan
Jared L. Zerbe
Rich Perego
Fariborz Assaderaghi
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Citations (4)
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
2009
VLSIC | Symposium on VLSI Circuits
Hae-Chang Lee
Kun-Yung Ken Chang
Jung-Hoon Chun
Ting Wu
Yohan Frans
Brian S. Leibowitz
Nhat Nguyen
T. J. Chin
Kambiz Kaviani
Jie Shen
Xudong Shi
Wendemagegnehu T. Beyene
Simon Li
Reza Navid
Marko Aleksic
F.S. Lee
Fredy Quan
Jared L. Zerbe
Rich Perego
Fariborz Assaderaghi
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Citations (3)
1