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Y. R. Lin
Y. R. Lin
TSMC
Electronic engineering
CMOS
Jitter
Electrical engineering
Engineering
3
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4
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Enhancement mode strained (1.3%) germanium quantum well FinFET (W Fin =20nm) with high mobility (μ Hole =700 cm 2 /Vs), low EOT (∼0.7nm) on bulk silicon substrate
2014
IEDM | International Electron Devices Meeting
Ashish Agrawal
Michael Barth
G. B. Rayner
V. T. Arun
Chad M. Eichfeld
Guy P. Lavallee
Shih-Ying Yu
X. Sang
S. Brookes
Yuanxia Zheng
Yi-Jing Lee
Y. R. Lin
C.-H. Wu
Chih-Hsin Ko
James M. LeBeau
Roman Engel-Herbert
Suzanne E. Mohney
Yee-Chia Yeo
Suman Datta
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At 10 GHz and Beyond
2004
Y. J. Wang
Y. R. Lin
Sorin P. Voinigescu
Mihai Tazlauanu
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Foundry 0.13 /spl mu/m CMOS modeling for MS//spl mu/wave SOC design at 10 GHz and beyond
2004
RFIC | Radio Frequency Integrated Circuits Symposium
M.T. Yang
Tzu Jin Yeh
Y. J. Wang
Patricia P. C. Ho
Y. R. Lin
Darryl Kuo
S.P. Voinigescu
M. Tazlauanu
Y. T. Chia
K. L. Young
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Citations (2)
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