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Nobuo Kojima

IBM

3

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49

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A 1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache

2000 VLSIC | Symposium on VLSI Circuits
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A 1 GHz single-issue 64 b PowerPC processor

2000 ISSCC | International Solid-State Circuits Conference
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“Timing closure by design,” a high frequency microprocessor design methodology

2000 DAC | Design Automation Conference
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