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T. Miyashita

Applied Materials

3

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3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors

2019 IEDM | International Electron Devices Meeting
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Highly conductive metal gate fill integration solution for extremely scaled RMG stack for 5 nm & beyond

2017 IEDM | International Electron Devices Meeting
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