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Hye Young Lee
Hye Young Lee
SK Hynix
Computer science
Electronic engineering
DDR4 SDRAM
Cyclic redundancy check
Architecture
2
Papers
14
Citations
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A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture
2012
ISSCC | International Solid-State Circuits Conference
Kibong Koo
Sunghwa Ok
Yonggu Kang
Seung-bong Kim
Choung-Ki Song
Hye Young Lee
Hyungsoo Kim
Yongmi Kim
Jeonghun Lee
Seunghan Oak
Yo-Sep Lee
Jungyu Lee
Joongho Lee
Hyungyu Lee
Jae-Min Jang
Jongho Jung
Byeongchan Choi
Yong-Ju Kim
Youngdo Hur
Yunsaing Kim
Byongtae Chung
Yongtak Kim
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Citations (12)
A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs
2011
ISCAS | International Symposium on Circuits and Systems
Jinyeong Moon
Hye Young Lee
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Citations (2)
1