A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs

In this paper, a new low-jitter dual-loop delay locked loop (DLL) with multi digitally controlled delay lines (DCDLs) is proposed. With this proposal, a limitation on unit delay amount is drastically reduced; hence the maximum frequency that a dual-loop DLL supports can be easily expanded into GHz range. Also, the invalidation system employed in the reference delay loop helps reduce the jitter in the final output clock of the DLL.