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Bor-Doou Rong
Bor-Doou Rong
Computer science
Dram
Electronic engineering
Architecture
Computer hardware
5
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5
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0
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2024
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Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns
2021
VLSIC | Symposium on VLSI Circuits
Nicky Chau-Chun Lu
Chun Shiah
Juang-Ying Chueh
Bor-Doou Rong
Wei-Jr Huang
Ho-Yin Chen
Cheng-Nan Chang
Chang Chia-Wei
Tzung Shen Chen
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Session 25 Overview: DRAM Memory Subcommittee
2021
ISSCC | International Solid-State Circuits Conference
Dong Uk Lee
Bor-Doou Rong
Kyu-hyoun Kim
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SPARR: Spintronics-based private aggregatable randomized response for crowdsourced data collection and analysis
2020
Computer Communications
Yao-Tung Tsou
Hao Zhen
Sy-Yen Kuo
Ching-Ray Chang
Akio Fukushima
Bor-Doou Rong
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A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems
2019
VLSIC | Symposium on VLSI Circuits
Chun Shiah
C N Chang
Richard Crisp
C.P. Lin
C.N. Pan
C P Chuang
H. L. Chen
S.H. Jheng
T. F. Chang
W J Huang
K. C. Ting
Rick Dai
W. M. Huang
Bor-Doou Rong
Nicky Chau-Chun Lu
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A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs
2015
VLSIC | Symposium on VLSI Circuits
Pei-Wen Luo
Chi-Kang Chen
Yu-Hui Sung
Wei Wu
Hsiu-Chuan Shih
Chia-Hsin Lee
Kuo-Hua Lee
Ming-Wei Li
Mei-Chiang Lung
Chun-Nan Lu
Yung-Fa Chou
Po-Lin Shih
Chung-Hu Ke
Chun Shiah
Patrick F. Stolt
Shigeki Tomishima
Ding-Ming Kwai
Bor-Doou Rong
Nicky Chau-Chun Lu
Shih-Lien Lu
Cheng-Wen Wu
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Citations (2)
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