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Patrick F. Stolt
Patrick F. Stolt
Intel
Computer science
Parallel computing
CAS latency
Latency (engineering)
Embedded system
5
Papers
11
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Probabilistic replacement strategies for improving the lifetimes of NVM-based caches
2017
Elizabeth Reed
Alaa R. Alameldeen
Helia Naeimi
Patrick F. Stolt
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Citations (5)
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache
2017
ISSCC | International Solid-State Circuits Conference
Tah-Kang Joseph Ting
Gyh-Bin Wang
Ming-Hung Wang
Chun-Peng Wu
Chun-Kai Wang
Chun-Wei Lo
Li-Chin Tien
Der-Min Yuan
Yung Ching Hsieh
Jenn-Shiang Lai
Wen-Pin Hsu
Chien-Chih Huang
Chi-Kang Chen
Yung-Fa Chou
Ding-Ming Kwai
Zhe Wang
Wei Wu
Shigeki Tomishima
Patrick F. Stolt
Shih-Lien Lu
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Citations (4)
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs
2015
VLSIC | Symposium on VLSI Circuits
Pei-Wen Luo
Chi-Kang Chen
Yu-Hui Sung
Wei Wu
Hsiu-Chuan Shih
Chia-Hsin Lee
Kuo-Hua Lee
Ming-Wei Li
Mei-Chiang Lung
Chun-Nan Lu
Yung-Fa Chou
Po-Lin Shih
Chung-Hu Ke
Chun Shiah
Patrick F. Stolt
Shigeki Tomishima
Ding-Ming Kwai
Bor-Doou Rong
Nicky Chau-Chun Lu
Shih-Lien Lu
Cheng-Wen Wu
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Citations (2)
Automatically scrubbing ECC errors in memory via hardware
1995
Mark A. Gonzales
Thomas J. Holman
Patrick F. Stolt
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Method and apparatus for automatic removal of ECC memory errors by means of hardware
1995
Mark A. Gonzales
Thomas J. Holman
Patrick F. Stolt
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