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Tzung Shen Chen

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Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns

2021 VLSIC | Symposium on VLSI Circuits
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Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

2015 IEEE Journal of Solid-state Circuits
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3D stackable vertical-gate BE-SONOS NAND flash with layer-aware program-and-read schemes and wave-propagation fail-bit-detection against cross-layer process variations

2013 VLSIC | Symposium on VLSI Circuits
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