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Peter Biolsi

35

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46

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Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

2021 IEEE Electron Device Letters
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LER reduction strategies for EUV self-aligned double patterning (SADP)

2021
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Line edge roughness reduction for EUV self-aligned double patterning by surface modification on spin-on-carbon and tone inversion technique

2021
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Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

2021
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Isotropic plasma free Si trim for FinFET to GAA device architectures (Conference Presentation)

2020
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Plasma process of Silicon Germanium alloy: molecular dynamics simulation study (Conference Presentation)

2020
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Improvement of self-aligned dual patterning using spin-on-carbon mandrel

2020
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A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

2019 IEDM | International Electron Devices Meeting
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Line roughness improvements on EUV 36nm pitch pattern by plasma treatment method

2019
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Integrated self-aligned quadruple patterning flow for sub-7nm application

2019
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