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Hiroshi Gojohbori
Hiroshi Gojohbori
Toshiba
Electronic engineering
CMOS
Static random-access memory
Engineering
Shallow trench isolation
4
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10
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Trench isolation technology with 1 /spl mu/m depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 /spl mu/m n/sup +p/sup +/ spacing
1994
VLSIT | Symposium on VLSI Technology
K. Ishimaru
Hiroshi Gojohbori
Hidetoshi Koike
Yukari Unno
M. Sai
F. Matsuoka
Masakazu Kakumu
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Citations (5)
High-Density Full-CMOS SRAM Cell Technology with a Deep Sub-Micron Spacing between nMOS and pMOSFET (Special Section on High Speed and High Density Multi Functional LSI Memories)
1994
IEICE Transactions on Electronics
Fumitomo Matsuoka
K. Ishimaru
Hiroshi Gojohbori
Hidetoshi Koike
Yukari Unno
Manabu Sai
Toshiyuki Kondo
Ryuji Ichikawa
Masakazu Kakumu
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Citations (1)
Trench isolation technology with 1 μm depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 μm n+/p+ spacing
1994
K. Ishimaru
Hiroshi Gojohbori
Hideki Koike
Yoshinobu Unno
Maamar Sai
F. Matsuoka
Masakazu Kakumu
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High performance BiCMOS technology design for sub-10 ns 4 Mbit BiCMOS SRAM with 3.3 V operation
1992
VLSIT | Symposium on VLSI Technology
Takeo Maeda
Hiroshi Gojohbori
K. Inoue
K. Ishimaru
Azuma Suzuki
H. Kato
Masakazu Kakumu
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Citations (4)
1