Old Web
English
Sign In
Acemap
>
Paper
>
Trench isolation technology with 1 μm depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 μm n+/p+ spacing
Trench isolation technology with 1 μm depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 μm n+/p+ spacing
1994
K. Ishimaru
Hiroshi Gojohbori
Hideki Koike
Yoshinobu Unno
Maamar Sai
F. Matsuoka
Masakazu Kakumu
Keywords:
Shallow trench isolation
Trench
Electronic engineering
Static random-access memory
CMOS
Geology
Correction
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]