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J.R. Raguet
J.R. Raguet
STMicroelectronics
Logic gate
Electrical engineering
Electronic engineering
Architecture
Bitwise operation
4
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8
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A Dual-Gate Memory Cell with Two Inter-poly Oxides
2008
The Japan Society of Applied Physics
J.R. Raguet
P. Calenzo
R Laffont
Damien Deleruyelle
R. Bouchakour
V. Bidal
Arnaud Regnier
Stephan Niel
Pascal Fornara
J.M. Mirabel
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Investigation of a new three bits cell concept
2008
NVMTS | Non-Volatile Memory Technology Symposium
J.R. Raguet
P. Calenzo
Damien Deleruyelle
R. Laffont
A. Guiraud
R. Bouchakour
V. Bidal
P. Boivin
Stephan Niel
Pascal Fornara
J.M. Mirabel
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New EEPROM concept for single bit operation
2007
ISDRS | International Semiconductor Device Research Symposium
J.R. Raguet
V. Bidal
Arnaud Regnier
J.M. Mirabel
R. Laffont
R. Bouchakour
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New EEPROM concept for single bit operation
2007
ISDRS | International Semiconductor Device Research Symposium
J.R. Raguet
R. Laffont
R. Bouchakour
V. Bidal
Arnaud Regnier
J.M. Mirabel
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Citations (7)
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