A Dual-Gate Memory Cell with Two Inter-poly Oxides

A new dual-gate memory cell with two different inter-poly oxides is presented in this paper. This cell allows high density memory application and a cell programming only with the dual-gate without high bias on drain or source compared to standard electrical erasable and programmable read-only memory (EEPROM). Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 48%. The specificity is to use a dual-gate to program the cell with two different ways of charge injection and perform the memory operations without high bias on drain and also without select transistor. Thus this cell can be shrunk more easily and its lifetime can be improved because the band to band tunneling stress due to high drain potential is eliminated. Moreover, this dual-gate cell can become an adjustable threshold voltage transistor.