Test Architecture for Fine Grained Capture Power Reduction

Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, over- heating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction-approaching 100% for multiple patterns.