Asymmetric Keep-Out Zone of Through-Silicon Via Using 28-nm Technology Node

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( $\vert \sigma _{r}\vert )$ does not equal to that of tangential stress ( $\vert \sigma _{\theta }\vert )$ on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.