Increase of SiC Substrate Resistance Induced by Annealing

We report here an anisotropic increase in SiC bulk resistivity by annealing at 1150 °C, and discuss the implications for SiC devices. The increase in resistivity is resistivity dependent and can be (at least) partially reversed by a subsequent anneal at higher temperature. Ideal device performance is achievable with appropriate annealing steps during device processing.