A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process
2008
This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40 nm DRAM process that has a fan-out of four-inverter delay (FO4) of 45 ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, and a data-dependent regulator. The transceiver has measured random jitter of 380 fs rms at the transmitter output and BER -14 while consuming 8 mW/Gb/s.
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