III-V Devices for Advanced CMOS

However, there are a number of challenges associated with introducing III-V materials for VLSI. From an economic standpoint it must be possible to generate substrates by growing high quality, low defect III-V layers on 300mm (or even potentially 450mm) Si wafers in order to leverage state-of-the-art technology. If Ge is indeed to be used as the pMOS device to the III-V nMOS, then both materials will need to integrated on the same wafer and suitable complementary processing techniques developed for both. Suitable passivation methodologies for the gate stack need to be found as III-V/oxide interfaces materials have higher Dit values than Si. GaAs/amorphous oxide interfaces show two large localized peaks at around mid-gap energies. With the exception of the GaAs/Ga2O3-GaGdOx system, passivation techniques reported to date have not been successful in suppressing these peaks and as a consequence the GaAs-amorphous oxide interface cannot be inverted with more commonly used high-k dielectrics such as Al2O3 or HfO2. More promising results have been obtained from the InGaAs-Al2O3 interface. In this case an asymmetric distribution is found , with reasonably low densities of interface states close to the conduction band and a very strong increase of states towards the valence band. The interface state peaks appear to be donor-like and are uncharged when the Fermi level is close to the conduction band. This allows for a relatively large ION but the states near the valence band cause a degradation in the subthreshold slope and IOFF of these devices.