Reduction of thermal induced pattern loading and device sensitivity by various rapid thermal processing models

Beyond 65nm node, pattern loading effect (PLE) in conventional RTP (front-side heating) has been emerged as a major yield killer. Different pattern and deposited film property strongly influence thermal absorption and emission at the integration stage of the spike anneal (e.g., STI, poly, and nitride spacers) lead to significant temperature differences across each die. Several methods for reducing the temperature variation have been reported, such as layout modifications and the application of absorption layers. By using these methods, significant improvements can be obtained, but the limitation is layout flexibility and increasing extra cost. The present study provides a simple way to mitigate the PLE problem by various RTP models (A: front-side heating; B: back-side heating; C: dual-side heating). A remarkable Ion distribution improvement can be achieved for 40nm & 28nm technology (15%∼20% intra-die variation reduction). In addition, we also find out the correlation between RTP thermal profile & device sensitivity (Ion, DIBL, Cov, etc.): shorter residence time reduces ∼50% device Ion sensitivity. It also helps to understand the device variation from different thermal conditions.