Alternating phase shifting mask implementation to 0.1-μm logic gates

Double exposure alternating phase-shift mask (alt-PSM) technology with ArF exposure was used in the 0.1 micrometers technology node for patterning logic devices with polysilicon gates ranging from 110nm to 60nm. A dual-trench mask fabrication process was developed in-house at TSMC, and controls for phase accuracy and intensity balance were established. Optical proximity correction (OPC) was performed on both binary masks and alt-PSM. Interactions between the binary and the PSM exposures were taking in to accounted during the correction. Using Model based OPC and a single calibrated resist model, the critical dimensions (CD) linearity can be ideally matched to the designed CD for duty ratio >= 1:1.5 for polygate logic product has been implemented exhibiting an enlarged DOF, good resist line edge roughness (LER), a d CD uniformity.