Study of 3D process impact on advanced CMOS devices

Through 3D-IC Integration is possible to put more transistors on the same footprint without the need to shrink transistor sizes. As for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing. In this work we introduce the several processes to generate 3D stacked devices. We focus on processes like TSV, wafer thinning, backside passivation, back side RDL (Re-Distribution Layer), front side and backside μbumping. We report on the characterization of the effects on transistor devices due to TSV proximity, wafer thinning and die stacking. The transistor devices are based on imec CMOS technology and are manufactured on 300mm diameter wafers. The wafers are fully processed with Front End of Line (FEOL), Back End Of Line (BEOL), wafer thinning on Si carrier, back-side wafer bumping, carrier de-bonding, dicing and final 3D-stacking. We report the main electrical characterizations done to identify the impact of typical 3D processes on CMOS devices. The characterizations are performed in-line (clean room compatible test equipment) and confirmed offline (standard testing equipment out of clean room environment). To characterize the process steps of interest, we use dedicated test structures that are measured before and after the process. The dedicated test structures are mainly measured after wafer front side processing (FEOL and BEOL) and tested again after wafer thinning and after die stacking. The measured variations (typically I ON currents) are later elaborated to illustrate the process effect. In case of 3D stacks, the characterization is executed for two-dies stacking. To have an assessment of the 3D stacking yield, the dies are connected by TSVs-μbumps in several daisy chain configurations.