TSV MEOL (Mid End of Line) and packaging technology of mobile 3D-IC stacking

Increasing demand for advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven semiconductor industry to develop more innovative and emerging advanced packaging technologies. Memory bandwidth has become a bottleneck to mobile processor performance and lower power consumption for high performance computing needs. To reduce obstacles, a revolution in device architecture and package technologies is require. 3D TSV (Through Silicon Via) stacking is to be one of the technologies that can meet those requirements. This paper mainly describes the 3D TSV MEOL process and packaging technology, especially TSV wafer process and thin die bonding process with Cu column bump on substrates. In order to prove the quality of this 3D package, some stress tests were conducted to evaluate the reliability on the package and board level. The innovative TSV MEOL process and flip chip assembly with micro Cu column contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structures which consisted of a 28 nm logic device and Wide I/O memory. The logic device was fabricated by via-middle process and accompanied with over 1200 TSVs, and 40 μm / 50 μm bump pitch layout. Advanced 300mm backside via reveal (BVR) process was developed with thin wafer handling and temporary bonding/debonding process. Thermocompression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. As reliability test items, temperature cycling test, high temperature storage test, humidity test, unbiased highly accelerated stress test and pressure cooker test were performed and passed JEDEC standard reliability tests as well as board level reliability test. After functional test with stacked 3D TSV with logic and Wide IO memory, 12.8 GB/s transmission and drastic I/O power saving compared to LPDDR3 were observed.