Substrate-dependent Copper Electroless Deposition

The performance requirements of interconnects at the level of 22 and 45 nm nodes for ultra-large scale integrated devices demands that back-end-of-the-line (BEOL) copper metallization have low electrical resistivity and high resistance to electromigration. Copper has been developed to replace the conventional aluminum-base metallization in the memory and logicdevice manufacturing process. It is due to its low resistivity (1.67μΩ·cm), high melting point (1,085 ), and high electromigration resistance. Typically, copper is deposited by chemical vapor deposition, sputtering, and electrochemical deposition on a barrier layer. Electroless copper plating, a technology already in-use for electronic packaging, has been used in the fabrication of copper onchip interconnects to fill features. In recent years, copper electroless deposition (ELD) has emerged as the most efficient way to fill nano features, which is based on the dual-damascene technology. Therefore, we can expect low process cost and high filling capability to ELD that comes in the next sequence. It is possible that electroless plating processes will offer significant advantages for future wiring structures in nano-scale materials fabrication of the metal nanowire for biosensor, ultra large scale integration (ULSI) and micro electromechanical system (MEMS). In ELD process, it requires the novel metal seed layer as a catalyst because copper is hardly electroplated directly on barrier layer TaN and TiN. Therefore, various deposition techniques such as acid solution, sputtering, MOCVD, and ionized cluster beam (ICB) have been proposed for the preparation of a thin metal seed layer for catalyst. However, with the shrink in dimensions of interconnections, it is getting more and more difficult to form a continuous sputtered the metal seed layer at side walls of fine holes, which results in voiding during electroless plating. In this work, we investigated Cu deposition in the electroless bath on various substrates. Palladium has been recently deposited on the copper barrier via atomic layer deposition and it is also an appropriate catalyst for the electroless deposition of copper. In a previous study, we examined Pd catalyst layer by atomic layer deposition (ALD) for high step coverage and good filling on TaN substrate [1,2]. In this work, palladium catalyst was deposited by ALD, the deposition chamber walls were kept at 75-80°C and the lines between the sublimation tube and the deposition chamber at 78°C to ensure no cold spots existed to condense Pd(hfac)2. During each deposition for Pd, 55 sccm Ar (99.999% Air Products) was flowed as a purge gas, 13 sccm Ar as a carrier gas for Pd(hfac)2, and 105.0 sccm H2 as a reducing gas. The pulse sequence was 15 seconds of PdII(hfac)2 followed by 8 seconds of ‘dead time’ with just 55 sccm Ar flowing as a purge gas, then 7 seconds of H2 to allow for a steady state in the plasma, and then 15 seconds of remote H2 plasma with 105.0 sccm H2 flow and 65W net forward power. The number of cycles for each deposition was 100. For the copper electroless process, ethylenediamine-tetraacetic acid (EDTA) was used as a chelating agent, glyoxylic acid as a reducing agent, and additional chemicals such as polyethylene glycol, 2,2’dipyridine and Re-610 as surfactant, stabilizer and antifoaming agent respectively. The characterizations of Cu films were carried out by using Field Emission Scanning Electron Microscopy (FESEM), X-ray Diffraction (XRD) X-ray photoelectron spectroscopy (XPS) and Rutherford backscattering (RBS). Cu was undertaken at 60°C with good adhesion to tantalum nitride and iridium with Pd as a catalytic layer. It has been proposed that Cu deposited on W and Pt is undertaken by a different mechanism without Pd by ALD. A typical XPS spectra (Fig.1), indicates that all the standard photoelectron lines of elemental Cu are present. It can be seen in FESEM image (Fig.2) that very fine copper grains coalesced to form a uniform coverage without dendrite formation.