Integrated arc suppression unit for defect reduction in PVD applications

Arcing between the target and plasma during PVD deposition causes substantial damage to the target and splats and other contamination on the deposited films. Arc-related damages and defects are frequently encountered in microelectronics manufacturing and contributes largely to reduced wafer yields. Arcing is caused largely by the charge buildup at the contaminated sites on the target surface that contains either nonconducting inclusions or nodules. Arc suppression is a key issue for defect reduction, yield improvement and for reliable high quality metallization. An Integrated Arc Suppression Unit (IASU) has been designed for Endura HP PVD TM sputtering sources. The integrated design reduces cable length from unit to source and reduces electrical energy stored in the cable. Active arc handling mode, proactive arc prevention mode, and passive by-pass arc counting mode are incorporated into the same unit. The active mode is designed to quickly respond to chamber conditions, like a large chamber voltage drop, that signals a arc. The self run mode is designed to proactively prevent arc formation by pulsing and reversing target voltage at 50 kHz. The design of the IASU, also called mini small package arc repression circuit--low energy unit (mini Sparc-le), has been optimized for various DC magnetron sources, plasma stability, chamber impedance, power matching, CE MARK test, and power dissipation. Process characterization with Ti, TiN and Al sputtering indicates that the unit has little adverse impact on film properties. Mini Sparc-le unit has been shown here to significantly reduce splats occurrence in Al sputtering. Marathon test of the unit with Ti/TiN test demonstrated the unit's reliability and its ability to reduce sensitivity of defects to target characteristics.