180nm FRAM reliability demonstration with ten years data retention at 125°C

Reliability of a 2T-2C, 448kbit FRAM embedded within 180nm CMOS is presented. The results indicate a 10-year, 125°C data retention capability for this technology. Further, sufficient signal margin remains for sensing following 260°C Pb-free solder reflow step demonstrating that code data can be stored through the board-attach process. A new margin test approach, which enables depolarization effects to be quantified, has been developed. A model to estimate device fail rate based on array size, word length, error correction circuitry and bit error rate is also described.