Enhancing a hierarchical, parallel electron beam data conversion processor toward 1 Gbit memory lithography

A new hierarchical, parallel electron beam (EB) data conversion system has been developed to be used in lithography for the fabrication of memories of 1 Gbit or more. The conversion system has been enhanced not only to meet EB writing requirements but also to cover new data processing capabilities required for critical dimension control and for optical resolution enhancement. The conversion system takes full advantage of the hierarchical, parallel technique and generates patterns for various EB lithography systems, including the EX‐8 mask writing system, EX‐8D wafer direct writing system, and MC‐100 defect inspection system. The interface with computer aided design (CAD) systems has been improved by realizing direct input from CADENCE Opus or Edge and from a design rule checker ENMA in addition to CALMA GDSII format. A design guide has been established to guarantee efficient, problem‐free hierarchical data conversion. Also, a new data compaction technique has been employed. The system is equipped with fun...