Line-edge roughness reduction and CD slimming using hardback processing

Tight control of very small transistor gate CDs is one of the most difficult problems in advanced device patterning. Line-edge roughness on these small gate lines has become a serious issue with 193nm lithography and is only expected to worsen with 157nm and EUV lithography. Methods are needed that can minimize line-edge roughness while also enabling the patterning of small gate features. We have analyzed the use of a simple and manufacturable post-develop bake step, a 'hardbake', that controllably reduces both gate resist CDs and to line-edge roughness. Hardbake resist shrinkage is a well-known phenomena from earlier Novolak resist processing, but has not been investigated for chemically amplified resists as much as other CD slimming techniques. Our tests have been performed for different chemically amplified 193nm and EUV-type (essentially reformulated 248nm) resists. The results of our experiments show considerable potential for certain types of resists to provide gate CD control benefits from either roughness reduction or CD slimming.