The rapid growth of data bandwidth required between logic and memory chips for next generation device nodes is progressively pushing low I/O count serial busses to their limits. To further satisfy this increasing need for high data rates, wider I/O count busses are now being developed and established. Over the past years, various Fan-Out Wafer-Level-Packaging (FOWLP) approaches have been developed to answer the needs mentioned above and the increasingly demanding function integration on package. Imec has been working on a novel 300mm Fan-Out Wafer-Level-Packaging concept that enables 20μm pitch interconnect density. Results from experiments demonstrates wafer bow below 500μm after molding on silicon substrate with ultra-low die shift with maximum die to carrier mismatch below 10μm on full 300mm wafers. Further warpage and die shift evolution are expected depending on the process steps the wafers must go through and will be further discussed.
In this work, we demonstrate a completely functional $\mathbf{2}\ \boldsymbol{\mu} \mathbf{m}$ pitch RDL with two interconnecting metal layers and discuss results targeting a $\mathbf{1}\ \boldsymbol{\mu} \mathbf{m}$ pitch. Polymer-based RDL interconnects are a key enabler for advanced packaging utilized for the integration of heterogeneous systems. A growing number of components and increasing bandwidth needs have driven the number of layers and RDL critical dimensions (CD) ever lower [1]–[4]. In addition, areal densities for the vertical via interconnects are demonstrated down to 4 by $\mathbf{4}\ \boldsymbol{\mu} \mathbf{m}$ , twice the line pitch. Further scaling enables higher IO capabilities overlapping Back End of Line (BEOL) metallization capabilities.
This study investigates creation of 1.0μm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is that the Cu overburden removal does not affect the quality of the embedded Cu lines. In comparison, for a semi-additive process the Cu seed etch affects the final dimensions of the RDL lines [1]. Damascene processing of RDL will also result in a flat wafer surface which greatly improves the lithographic performance for subsequent layers. Finally, the Cu line is surrounded on the sides and bottom by a Ti barrier layer which provides a Cu diffusion barrier for enhanced reliability [2,3]. The completed 1.0μm RDL damascene process is evaluated using a test chip design that includes metrology structures for in-line monitoring and CDSEM measurements, and comb and serpentine electrical test structures. The electrical results for the damascene process show significant advantages compared to the semi-additive process.
This paper presents the performance of a MEMS zero-level chip cap package implemented with through-the-cap vertical interconnects. The interconnect as well as the hermetic bond and sealing are established using flip-chip thermo-compression bonding by creating a copper-tin to gold metallic (solder) joint. The hermeticity of the packages is assessed via electrical measurements of encapsulated MEMS resonators and the RF performance of 3D interconnects is evaluated via microwave measurements of integrated coplanar waveguides. Design guidelines imposed by concurrent requirements of the flip-chip assembly process and the RF performance are discussed. The developed technology for the MEMS cap uses CMOS-compatible materials and the CMOS fabrication process.
A Kelvin contact resistance test structure has been developed for accurate measurement of highly-doped, shallow n/sup +/ and p/sup +/ implantations, which are self-aligned to the contact window. Here the structure has been integrated, without additional processing, in a 30 GHz washed-emitter-base n-p-n bipolar process, for the purpose of monitoring the emitter contact resistance. Diffusion taps to the emitter have been made with the phosphorus collector-plug implantation. Phosphorus evaporation from the contact window during the anneal step and the low sheet resistance of the collector-plug implantation, together with the overall design of the test structure, assure a very accurate determination of the emitter contact resistance even in situations where complete junction isolation of the diffusion taps is not directly possible. Results are presented for the optimization of the emitter anneal cycle with respect to the emitter contact resistance.
Over the last years, 3D TSV technology and 3D stacking have moved into the preproduction and yield ramp phase. The characterization of many of the different critical modules within the 3D stacking integration flows is becoming more and more crucial. Microbump dimensions are being scaled down to the pitch of 20μm and below. This scaling is required in order to achieve higher interconnect densities. For yielding vertical interconnects in die-to-die and die-to-wafer stacking, highly accurate and repeatable measurements and inspections of microbumps are an absolute must for this technology to become a viable industrial option. Microbump process control is usually a hybrid approach of inspecting the full wafer including all microbumps and specific microbump metrology. This eventually enables correct die classification and selection of known good die for further integration in 3D packages. Prior to being able to classify and disposition die based on microbump integrity, yield critical defect types need to be identified, defect mechanisms need to be understood and dimensional features impacting further processing need to be characterized. This paper addresses these requirements and elaborates on the applied defect learning methodology based on a significant amount of microbump process monitor wafers. Yield loss by every defect type was quantified and root causes for these yield critical defect types were discovered. From this analysis, further process improvement projects can be initiated, parameters for statistical process control derived and known good die for yielding die-to-die and die-to-wafer stacking can be identified and separated from failing die.
As the need for higher degrees of function integration on chips continues to rise, chip-to-chip connection density exponentially increases. The continuous push for denser interconnects has brought conventional FO-WLP to its limit. A novel FO-WLP concept has been proposed to enable 20-μm pitch interconnect chip-to-chip. To achieve this density and to further scale it down, a critical element is ultra-precise die-to-die positioning in the micron range. Advances in temporary bonding materials and carrier systems are required to enable such applications.
High power excimer laser annealing is used to activate dopants implanted in polysilicon layers. Sheet resistances as low os 50 /spl Omega///spl square/ are achieved for thin polysilicon layers on oxide, and low ohmic contacts have been produced to implanted junctions elevated by a polysilicon layer. The influence of the thickness of either the poly or the underlying oxide is evaluated.
Reliability results obtained on a photosensitive polymer-based redistribution layer (RDL) process with two-metal layers and a target pitch below 4 μm are presented. Fully processed samples have been subjected to 1000 h of high-temperature storage (HTS) performed at 150 °C when a second set of samples endured a temperature-humidity (TH) stress executed at 85 °C and 85 % RH. A thermal cycling (TC) stress between - 50 ° C and 125 °C for 1000 cycles was also performed on a third sample set. After 1000 h spent at 150 °C, an increase in the metal line resistivity resulting from copper oxidation by atmospheric oxygen diffusing through the polymer is observed. The oxidation of the top part of the metal lines is further confirmed by failure analyses performed on the stressed samples. Eight different polymers used as a potential capping solution to block the diffusion of oxygen toward the metal lines are investigated. The most promising approach for a reliable polymer-based RDL process involves the use of a mold layer.
The recent developments of wafer-to-wafer bonding technology based on direct assembly of inorganic dielectric materials is offering a path for the continuous need for higher integration density and lower interconnect pitches. However, numerous applications could benefit of a higher degree of design flexibility offered by a die-to-wafer approach. The achievement of high yielding die-to-wafer bonding with micron range die overlay is an essential element to unlock the potential of heterogeneous integration.
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