Enabling Ultra-Thin Die to Wafer Hybrid Bonding for Future Heterogeneous Integrated Systems
Alain PhommahaxaySamuel SuhardPieter BexSerena IacovoJohn SlabbekoornFumihiro InoueLan PengKoen KennesErik SleeckxGerald BeyerEric Beyne
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Abstract:
The recent developments of wafer-to-wafer bonding technology based on direct assembly of inorganic dielectric materials is offering a path for the continuous need for higher integration density and lower interconnect pitches. However, numerous applications could benefit of a higher degree of design flexibility offered by a die-to-wafer approach. The achievement of high yielding die-to-wafer bonding with micron range die overlay is an essential element to unlock the potential of heterogeneous integration.Keywords:
Wafer Bonding
Wafer-level packaging
Wafer-scale integration
Die preparation
It is well known that the packaging of electronic devices is of paramount importance, none more so than in MEMS were fragile mechanical elements are realized. Among the different approaches, wafer to wafer bonding guarantees the advantages of the wafer scaling and provides protection of the devices during the final phase of fabrication. Direct bonding, also known as fusion bonding, is seldom implemented in MEMS fabrication due to the high surface quality required, the high temperature involved and the compulsory wet activation process. In this paper a direct bonding process for MEMS inertial sensor without the need of any wet activation step is presented.
Wafer Bonding
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Anodic bonding
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Wafer backgrinding
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In this paper, the demonstration of test vehicle by two kinds of process flows noted as "C4 first" and "C4 last", which integrate chips on mold-based, Cu via wafer with glass carriers, are presented. Their warpage behavior during wafer-form integration will be experimentally and numerically evaluated, and also compared with wafer warpages of 2.5D assembly which applied Si interposer with TSV (through Si via). The C4-first flow is to attaching chips on wafers where the C4 bumps have been completed between mold layer and glass carrier. This flow is similar to 2.5D manufacturing process that the Si interposer was temporarily bonded on a carrier which can suppress the interposer warpage variation during reflow process. The temporary glue is required to protect the C4 bumps during chip on wafer procedures. In regarding to the cycle time and cost, the flow to complete C4 after chips attaching will be further studied. The processed induced u-bump (micro-bump) and u-pad (micro-pad) shift post jointing are observed to be larger than that in 2.5D flow. In the manufacturing process of molded wafer, the high CTE glass carriers are used to reduce CTE mismatch between molding compound and carrier. The significant wafer warpage changing from concave to convex shape was observed after chips attaching on the wafer. And the warpage will be further increased after underfilling and molding processes. To well predict and address the warpage trend, the finite element analyses are carried out to understand the process-induced warpage behaviors, and thus to select better material and process parameter. The key parameters affecting wafer warpages like material properties of molding compound, glass carrier and top-mold thickness are determined by finite element simulation. In light of the handing procedure of wafer form assembling equipment, the preferred wafer warpage shape is determined by experimental results. Finally, the test vehicle have been assembled with substrate as well. The chip module warpage in 2.5D structure is about double than that with molding interposer at 230°C and reversed direction in a convex shape, which is different from molding chip module.
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This paper presents the fabrication steps of a MEMS package based on silicon interposer wafers with copper filled TSVs and bonded cap wafers for hermetic sealing of resonator components. All processes were performed at 200 mm wafer level. For interposer fabrication a standard process flow including silicon blind hole etching, isolation, copper filling, wafer front side redistribution, support wafer bonding, wafer thinning, and TSV backside reveal was applied. As interposer backside metallization, appropriate I/O terminals and seal ring structures were deposited by semi-additive Au and Au+Sn electro plating. Following, getter material was deposited onto the interposer wafers which were 90 μm thick and still mounted onto carrier wafers. Subsequently, the I/O terminal pads of the interposer were stud bumped and finally more than 5000 quartz resonator components were assembled onto each interposer wafer by Au-Au direct metal bonding. The cap wafer was equipped with 200 μm deep dry etched cavities and electro plated Au seal rings around them. Finally, both cap and interposer wafers were bonded together using a wafer to wafer bonder and an adapted AuSn soldering process scheme. In a last step, the carrier wafer was removed from the former front side of the interposer wafer and wafer level testing was performed. From a total of 4824 tested devices we found that more than 75 % were sealed properly under vacuum. The getter appears to be effective leading to ~0.1 mbar equivalent air pressure and cavities without getter appear to reach residual air pressure between 1-2 mbar. The used fabrication processes and final results will be discussed detailed in this manuscript.
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This paper describes techniques for the miniaturized, low-cost wafer level chip-scale packaging of MEMS based system in packages (SiPs). The approaches comprise permanent bonding of cap structures using adhesives or solder onto a passive or active silicon wafer which is populated with MEMS components or which is itself a MEMS wafer. The paper addresses different options for manufacturing of lid or cap structures and their subsequent bonding to the partner wafer. Different technologies like bonding of full area cap wafers as well as partial capping approaches based on reconfigured cap structures on a help wafer or cap structures created on a compound wafer are presented. Examples like the selective capping process for RF-MEMS switches are discussed in detail. All processes were performed at 200 mm wafer scale.
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In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.
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In this letter, an approach to the redistribution of electrical interconnections is investigated for potential application in 3-D wafer-level packaging. A cap wafer with silicon bumps and electrical feedthroughs is bonded together with a device wafer using wafer-level glass-frit bonding technology. During the bonding process, the mechanical bond is performed by glass-frit bonding to form hermetic packaging. Simultaneously, the silicon bumps provide close contact for the electrical feedthroughs on the cap wafer and the metal pads on the device wafer, on which a gold-aluminum eutectic is formed to achieve electrical interconnections between the cap wafer and the device wafer. Moreover, the silicon bumps provide a way to control well the height of the bonding materials. This process not only realizes a wafer-level hermetic sealing but also achieves the redistribution of electrical interconnections. Application of this approach for a high performance MEMS resonator is demonstrated, which illustrates the feasibility of this process.
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In this paper, a 3D wafer-level hermetical packaging solution for micro-electromechanical-system (MEMS) is presented. The MEMS wafer is sandwiched between a top glass wafer and a bottom Si substrate wafer. With the assistance of a gold intermediate layer, the bottom Si wafer is hermetically sealed to the MEMS wafer with 3D electric feed-through connecting the metal pads on MEMS wafer with solder balls or bonding pads on bottom wafer for flip chip process. The bond strength is higher than 5 MPa.
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Wafer-level packaging
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A wafer-level chip-scale packaging scheme that can withstand temperatures of 600°C and above in long-term operation is proposed. The package comprises a SOI case and a cap wafer. In the device layer of the SOI wafer, flexible springs are formed to fix target chips inside the case, so that the influence of thermal stress can be minimized. The two components are joined together through wafer bonding process under vacuum condition. Electric connection is established through Pt metallized via in SOI. Initial test results confirm the feasibility of the method.
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The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 /spl mu/m in thickness, a crucial factor for use in various size sensitive electronic products.
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