A camel diode (CD) gamma-ray dosimeter with dual semifloating gates (SFGs) is presented. The SFG diode performs the function of collecting holes accumulated in the potential hump of CD, and hence controls the barrier height. With the silicon depletion instead of oxide as sensitive area, the sensitivity of the dosimeter is enhanced, while the volume is reduced compared with the conventional dosimeters. Moreover, the dosimeter requires only 2 V bias to reset within 1 ms. The numerical simulation has been carried out with Sentaurus TCAD. As a result, a linear dependence of threshold voltage on absorbed dose of the gamma rays was obtained with a sensitivity of 143 mV/Gy. Due to its high sensitivity, low power, and convenient resetting operation, the design is highly suitable for radiotherapy applications.
This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance ( R on,sp ). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field ( E -field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that R on,sp of the modified structure, and breakdown voltage ( V BR ) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit ( FOM=VBR2/Ron,sp ) is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge ( Q gd ) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the V BR of the device without degradation of dynamic performance.
Abstract Reducing the scavenging capacity of reactive oxygen species (ROS) and elevating ROS production are two primary goals of developing novel sonosensitizers for sonodynamic therapy (SDT). Hence, ultrathin 2D Bi 2 MoO 6 –poly(ethylene glycol) nanoribbons (BMO NRs) are designed as piezoelectric sonosensitizers for glutathione (GSH)‐enhanced SDT. In cancer cells, BMO NRs can consume endogenous GSH to disrupt redox homeostasis, and the GSH‐activated BMO NRs (GBMO) exhibit an oxygen‐deficient structure, which can promote the separation of electron–hole pairs, thereby enhancing the efficiency of ROS production in SDT. The ultrathin GBMO NRs are piezoelectric, in which ultrasonic waves introduce mechanical strain to the nanoribbons, resulting in piezoelectric polarization and band tilting, thus accelerating toxic ROS production. The as‐synthesized BMO NRs enable excellent computed tomography imaging of tumors and significant tumor suppression in vitro and in vivo. A piezoelectric Bi 2 MoO 6 sonosensitizer‐mediated two‐step enhancement SDT process, which is activated by endogenous GSH and amplified by exogenous ultrasound, is proposed. This process not only provides new options for improving SDT but also broadens the application of 2D piezoelectric materials as sonosensitizers in SDT.
Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.
A novel PIN-junction gate 4H-SiC UMOSFET with integrated heterojunction (PJG-UMOSFET) is proposed and numerically studied. The integrated heterojunction diode effectively suppresses the conduction of the intrinsic PN diode in the reverse conduction state of PJG-UMOSFET. The device simulation results show that the on-resistance (Ron) of the device is reduced by about 20.5 % compared with the traditional SiC UMOSFET, and there is almost no specific conduction resistance decrease. The reverse recovery time (tπ) and reverse recovery charge (Qπ) are reduced by 42.1 % and 68.4 %, and the gate-to-drain charge is reduced by 41.2 %. In addition, a feasible manufacturing process method for the proposed device is provided.
This paper proposes a new breakdown-enhanced GaN MISFET with the architecture of double channel and P-buried layer, i.e. DCP-MISFET. The lower barrier and lower channel are connected with the drain, the lower two dimensional electron gas can improve the device electric field distribution between gate and drain, achieving an enhanced breakdown voltage (BV). At the same time, the P buried layer below the gate field plate can reduce the peak electric field around the gate field plate. The proposed simulated device with LGD=15 μm presents an excellent breakdown voltage of 2373 V. In addition, the ON-resistance (RON) of 15.07 Ω•mm and Baliga's figure of merit of 3.736 GW•cm-2 are achieved in the optimized DCP-MISFET. Compared with breakdown voltage 1547 V of the optimized field plate conventional GaN MISFET (FPC-MSIFET), the proposed device increases the breakdown voltage by 53.39% and the Baliga's figure of merit is enhanced by 133.89%.
'/%3e%3cuse xlink:href='%23a' transform='rotate(23.036 .093 25.536)'/%3e%3cuse xlink:href='%23a' transform='rotate(45.87 1.273 16.18)'/%3e%3cuse xlink:href='%23a' transform='rotate(69.945 .996 12.078)'/%3e%3cuse xlink:href='%23a' transform='rotate(20.66 -19.689 31.932)'/%3e%3c/svg%3e)
