A SiC LDMOS with electric field modulation by a step compound drift region
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LDMOS
LDMOS
High Voltage
Silicon dioxide
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The optimization of the floating-ring parameters and the breakdown voltage of a lateral DMOS (LDMOS) transistor using a single floating ring is presented. A first-order analytical approach is presented, showing the upper limit of the position of the ring, with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is also presented. The results, which support the analytical approach, allow the use of simple design rules for the implementation of high-voltage LDMOS transistors on a thick epitaxial layer. It is shown that improvements of breakdown voltage is obtained if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specific relationship. With a single ring, the breakdown voltage increases from 170 to 280 V for the same device area and to over 480 V if the area is allowed to increase by 25%.< >
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Transistor model
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Figure of Merit
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The breakdown voltage and on-resistance of a multi-RESURF LDMOS are studied numerically and analytically. The results are compared with those from the conventional LDMOS. Reduction of on-resistance by 23% is obtained for the multi-layer structure without degradation in the breakdown voltage. An analytical expression for the surface potential distribution of the multi-layer structure is derived which provides a useful mean to determine the breakdown voltage analytically in terms of the device parameters.
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Electric breakdown
Power MOSFET
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A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-μm technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage (V BD ) is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in V BD and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.
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Figure of Merit
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Depletion region
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It is shown that field rings in the drift region of LDMOS (lateral double diffused MOS) transistors can be used to reduce the electric field at the Si/SiO/sub 2/ interface and increase the breakdown voltage of the structure. A first order analytical approach shows the upper limit of the position of the ring with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2-D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is presented. The results, which support the analytical approach, allow the designer to use simple design rules for the implantation of high-voltage LDMOS transistors on thick epitaxial layers. A potential improvement of the breakdown voltage arises if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specified equation. Doubling the breakdown voltage is associated with a 25% increase in device area. The on-resistance depends mainly on the field ring position with respect to the channel. A good tradeoff between the breakdown voltage and on-resistance is obtained when the channel-ring distance is equal to the field plate length.< >
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In this paper, two kinds of robust 700V DR-LDMOS (Double RESURF LDMOS) using thin epitaxial technology has been realized for level shifter and switching applications. The P-TOP layer is introduced to reduce on-resistance while maintaining high breakdown voltage for switching applications, and to increase on-breakdown voltage using JFET resistance for level shifter. The result is that the breakdown voltage of the 700V LDMOS for level shifter is 900V with on-breakdown of over 650V. In terms of switching applications, we have adopted HVPWELL layer of rainbow shape at source corner region to reduce n-type charge of N-EPI region and achieved the breakdown voltage of over 750V.
LDMOS
JFET
High Voltage
Avalanche breakdown
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A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage (BV) of conventional super junction-LDMOS.The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance.Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars.In addition,the proposed device is compatible with smart power technology.
LDMOS
High Voltage
Depletion region
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Abstract The differences between N ‐ and N + buried layers in improving the breakdown voltage of RESURF (reduced surface field) LDMOSFETs (lateral double‐diffused metal‐oxide‐semiconductor field‐effect transistors) are discussed in this paper. Two concise RESURF criteria for LDMOS with a low‐doped fully depleted N ‐ buried layer (NBL) and a highly doped nondepleted N + floating layer (NFL) are developed by optimizing the lateral and vertical electric fields. The analytical solution quantitatively demonstrates the variation of the drift charge concentration and its dependence on the key NBL and NFL parameters. It also indicates that the NBL LDMOS achieves a superior tradeoff between specific on‐resistance ( R s,on )and breakdown voltage ( BV ) to the NFL LDMOS. The BV 2 / R s,on for NBL LDMOS is 3.1 MW/cm 2 , which is increased respectively by 93.8% and 40.9% compared with the single RESURF and NFL‐LDMOS.
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