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Sean Collins
Sean Collins
Motorola
Electronic engineering
Electrical engineering
Engineering
Transistor
Gate oxide
4
Papers
8
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0
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Gate-length- and threshold-voltage-dependent nonlinearity in the hot carrier DC lifetime extrapolation for sub-100-nm NMOS devices
1999
Sejal N. Chheda
Navakanta Bhat
Paul G. Y. Tsui
Suzanne Gonzales
Nigel Cave
Chong-Cheng Fu
Fred Huang
Amit Nangia
Philip Sung-Joon Choi
Sean Collins
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Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25 /spl mu/m CMOS technology for embedded applications
1998
IEDM | International Electron Devices Meeting
Navakanta Bhat
P. Chen
Paul G. Y. Tsui
A. Das
Mark C. Foisy
Y. Shiho
J. Higman
J.-Y. Nguyen
S. Gonzales
Sean Collins
D. Workman
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Performance, standby power, and manufacturability trade-off in transistor design consideration for 0.25-um technology
1998
Navakanta Bhat
H. Chuang
Paul G. Y. Tsui
R. Woodruff
J. Grant
R. Kruth
Asanga H. Perera
Stephen S. Poon
Sean Collins
D. Dyer
Veena Misra
I.Y. Yang
Suresh Venkatesan
Percy V. Gilbert
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Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay
1998
VLSIT | Symposium on VLSI Technology
I.Y. Yang
Percy V. Gilbert
C. Pettinato
S.G.H. Anderson
R. Woodruff
Veena Misra
Navakanta Bhat
Kimberly G. Reid
T. Lii
C. Yuan
D. Dyer
David L. O'Meara
Sean Collins
H. de
S. Veeraraghavan
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Citations (6)
1