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Chuan H. Liu

7

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Impact of Ti/TiN (Glue/Barrier Layer) Formation on Ultra-thin Gate Oxide Reliability (HCI and NBTI) for Deep Sub-micron CMOS Transistors

2003 The Japan Society of Applied Physics
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Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Sub-Micron pMOSFETs

2001 The Japan Society of Applied Physics
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Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

2001 IEDM | International Electron Devices Meeting
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High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

2001 IEDM | International Electron Devices Meeting
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Comparison and correlation of ESD HBM (human body model) obtained between TLPG, wafer-level, and package-level tests

2000 EOS/ESD | Electrical Overstress/Electrostatic Discharge Symposium
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An Efficient Process-Evaluation Method for Ultra-Thin Gate Oxides

1999 The Japan Society of Applied Physics
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Analysis of hot-carrier degradation in 0.25-/spl mu/m surface-channel pMOSFET devices

1999 VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
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