Old Web
English
Sign In
Acemap
>
authorDetail
>
Ruey-Bin Sheen
Ruey-Bin Sheen
TSMC
Phase-locked loop
Electronic engineering
Jitter
CMOS
Computer science
4
Papers
5
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (4)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
A 55.9-fs Integrated Jitter (100 kHz to 100 MHz) Hybrid LC-tank PLL in 5-nm FinFET using Programmable Phase Re-alignment and Dynamic Coarse Tuning
2021
Tsung-Hsien Tsai
Ruey-Bin Sheen
Sheng-Yun Hsu
Chih-Hsien Chang
R. Bogdan Staszewski
Show All
Source
Cite
Save
Citations (0)
A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment with 0.6 us Settling, 0.619 ps Integrated Jitter and -240.5 dB FoM in 7-nm FinFET
2020
Tsung-Hsien Tsai
Ruey-Bin Sheen
Chih-Hsien Chang
Kenny Hsieh
Robert Bogdan Staszewski
Show All
Source
Cite
Save
Citations (1)
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS
2020
VLSIC | Symposium on VLSI Circuits
Mao-Hsuan Chou
Ya-Tin Chang
Tsung-Hsien Tsai
Tsung-Che Lu
Chia-Chun Liao
Hung-Yi Kuo
Ruey-Bin Sheen
Chih-Hsien Chang
Kenny Hsieh
Alvin L. S. Loke
Mark Chen
Show All
Source
Cite
Save
Citations (0)
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW
2018
VLSIC | Symposium on VLSI Circuits
Tsung-Hsien Tsai
Ruey-Bin Sheen
Chih-Hsien Chang
Robert Bogdan Staszewski
Show All
Source
Cite
Save
Citations (4)
1