A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment with 0.6 us Settling, 0.619 ps Integrated Jitter and -240.5 dB FoM in 7-nm FinFET

All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit quantization noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain to cover frequency drift due to temperature variations. Further, in CP-PLLs, the reset pulse of phase detector must be wide for proper PLL functioning, but this sets a lower limit on reference spurs. We propose a hybrid-PLL in 7-nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL. We introduce periodical phase realignment by the reference clock, and ultra-short pulse for resetting the phase detector. The hybrid PLL covers 0.2-4 GHz and settles in 0.6 us. It emits low -52 dB reference spurs in the conventional mode, and 1.05 ps and 0.62 ps integrated jitter in the conventional and realignment modes, respectively.