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Ibe Hidefumi

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Rapid Recovery Technique from Soft Error of FPGAs in Information and Communication Apparatus

2015
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EMC Circuit Design and Jisso Design for System LSI -- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side

2009
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A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention

2008 Symposium on VLSI Circuits
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