Old Web
English
Sign In
Acemap
>
authorDetail
>
Haris Suhail
Haris Suhail
University of California, Los Angeles
Embedded system
Computer science
Process (computing)
Bottleneck
Interconnection
2
Papers
0
Citations
0
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (2)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor
2021
ECTC | Electronic Components and Technology Conference
Saptadeep Pal
Irina Alam
Krutikesh Sahoo
Haris Suhail
Rakesh Kumar
Sudhakar Pamarti
Puneet Gupta
Subramanian S. Iyer
Show All
Source
Cite
Save
Citations (0)
Designing a 2048-Chiplet, 14336-Core Waferscale Processor
2021
DAC | Design Automation Conference
Saptadeep Pal
Jingyang Liu
Irina Alam
Nicholas Cebry
Haris Suhail
Shi Bu
Subramanian S. Iyer
Sudhakar Pamarti
Rakesh Kumar
Puneet Gupta
Show All
Source
Cite
Save
Citations (0)
1