Old Web
English
Sign In
Acemap
>
authorDetail
>
Gerard van der Weide
Gerard van der Weide
NXP Semiconductors
Electronic engineering
Computer science
CMOS
Phase-locked loop
Linearity
5
Papers
70
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (5)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals
2013
ESSCIRC | European Solid-State Circuits Conference
Yu Lin
Kostas Doris
Erwin Janssen
A Athon Zanikopoulos
Alessandro Murroni
Gerard van der Weide
Hans Hegt
Arthur van Roermund
Show All
Source
Cite
Save
Citations (7)
GS/s AD Conversion for Broadband Multi-stream Reception
2013
Erwin Janssen
A Athon Zanikopoulos
Kostas Doris
Claudio Nani
Gerard van der Weide
Show All
Source
Cite
Save
Citations (0)
A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist
2011
ISSCC | International Solid-State Circuits Conference
Kostas Doris
Erwin Janssen
Claudio Nani
A Athon Zanikopoulos
Gerard van der Weide
Show All
Source
Cite
Save
Citations (34)
A 65 nm CMOS Inductorless Triple Band Group WiMedia UWB PHY
2009
ISSCC | International Solid-State Circuits Conference
Domine M. W. Leenaerts
Remco Cornelis Herman Van De Beek
J. Bergervoet
Harish Kundur
Gerard van der Weide
Ajay Kapoor
Tian Yan Pu
Yu Fang
Yu Juan Wang
Biju Joseph Mukkada
Hong Sair Lim
Madhu Kiran
Chun Swee Lim
Sorin Badiu
Alan Chang
Show All
Source
Cite
Save
Citations (29)
A fast-hopping single-PLL 3-band MB-OFDM UWB synthesizer
2006
ESSCIRC | European Solid-State Circuits Conference
Remco Cornelis Herman Van De Beek
Domine M. W. Leenaerts
Gerard van der Weide
Show All
Source
Cite
Save
Citations (0)
1