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S. Amina Naaz
S. Amina Naaz
Signal processing
Field-programmable gate array
Parallel computing
Carry-select adder
Multiplication
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FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture
2014
ICDCS | International Conference on Devices, Circuits and Systems
S. Amina Naaz
M. N. Pradeep
Satish Bhairannawar
Srinivas Halvi
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