Carry-select adder

In electronics, a carry-select adder is a particular way to implement an adder, which is a logic element that computes the ( n + 1 ) {displaystyle (n+1)} -bit sum of two n {displaystyle n} -bit numbers. The carry-select adder is simple but rather fast, having a gate level depth of O ( n ) {displaystyle O({sqrt {n}})} . In electronics, a carry-select adder is a particular way to implement an adder, which is a logic element that computes the ( n + 1 ) {displaystyle (n+1)} -bit sum of two n {displaystyle n} -bit numbers. The carry-select adder is simple but rather fast, having a gate level depth of O ( n ) {displaystyle O({sqrt {n}})} . The carry-select adder generally consists of two ripple carry adders and a multiplexer. Adding two n-bit numbers with a carry-select adder is done with two adders (therefore two ripple carry adders), in order to perform the calculation twice, one time with the assumption of the carry-in being zero and the other assuming it will be one. After the two results are calculated, the correct sum, as well as the correct carry-out, is then selected with the multiplexer once the correct carry-in is known. The number of bits in each carry select block can be uniform, or variable. In the uniform case, the optimal delay occurs for a block size of ⌊ n ⌋ {displaystyle lfloor {sqrt {n}} floor } . When variable, the block size should have a delay, from addition inputs A and B to the carry out, equal to that of the multiplexer chain leading into it, so that the carry out is calculated just in time. The O ( n ) {displaystyle O({sqrt {n}})} delay is derived from uniform sizing, where the ideal number of full-adder elements per block is equal to the square root of the number of bits being added, since that will yield an equal number of MUX delays.