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Hung C. Ngo

IBM

19

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392

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

2009 VLSIC | Symposium on VLSI Circuits
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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

2009 IEEE Journal of Solid-state Circuits
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Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

2008 IEEE Transactions on Very Large Scale Integration Systems
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Stable high-density FD/SOI SRAM with selective back-gate bias using dual buried oxide

2008 SOI | International SOI Conference
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IBM Research Report Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

2007
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Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

2007 IEEE Transactions on Electron Devices
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The Design and Implementation of a Low-Overhead Supply-Gated SRAM

2006 ESSCIRC | European Solid-State Circuits Conference
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Wide limited switch dynamic logic circuit implementations

2006 VLSID | International Conference on VLSI Design
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Back-Gate Controlled Wide Tunable Range Diode Voltage in Asymmetrical Double-Gate Devices

2006 SOI | International SOI Conference
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Controlled-load limited switch dynamic logic circuit

2005 ISQED | International Symposium on Quality Electronic Design
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