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Robert K. Montoye

IBM

51

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Energy Efficiency Boost in the AI-Infused POWER10 Processor

2021 ISCA | International Symposium on Computer Architecture
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Very Low Voltage (VLV) Design

2017 ICCD | International Conference on Computer Design
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Matrix-matrix multiplication on a large register file architecture with indirection

2014 HiPC | IEEE International Conference on High Performance Computing, Data, and Analytics
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1Mb 0.41 µm 2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing

2013 VLSIC | Symposium on VLSI Circuits
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Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure

2013 ICASSP | International Conference on Acoustics, Speech, and Signal Processing
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Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor

2012 HPCA | High-Performance Computer Architecture
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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

2011 CICC | Custom Integrated Circuits Conference
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Demonstration of CAM and TCAM Using Phase Change Devices

2011 IMW | International Memory Workshop
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Performance and power evaluation of an in-line accelerator

2010 CF | Computing Frontiers
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An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

2008 VLSIC | Symposium on VLSI Circuits
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