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Ajay Kumar Dadoria

Maulana Azad National Institute of Technology

27

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64

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Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

2021
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Design of Low-Power Dynamic Type Latch Comparator Using 18 nm FinFET Technology for SAR ADC

2021
- B. Hemalatha
- Ajay Kumar Dadoria
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Nanoscale: Low Power, Noise Tolerant Wide Fan-In Domino FinFET OR Logic

2018 Journal of Nanoelectronics and Optoelectronics
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Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

2018 Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems
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Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

2018 International Journal of Numerical Modelling-electronic Networks Devices and Fields
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Ultra-low power FinFET-based domino circuits

2017 International Journal of Electronics
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Ultra low power adiabatic logic using diode connected DC biased PFAL logic

2017 Advances in Electrical and Electronic Engineering
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Low power high speed 1-bit full adder circuit design in DSM technology

2017
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Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

2017 Journal of Computational Electronics
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Leakage Reduction by Using FinFET Technique for Nanoscale Technology Circuits

2017 Journal of Nanoelectronics and Optoelectronics
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