Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

Power dissipation, propagation delay and noise are major issues in digital circuit design. In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for 8 and 16 input OR gates are designed and simulated using existing and proposed techniques in FinFET technology. In this paper utilize the property of FinFET on domino circuit in order to improve the overall performance of the circuit. Here all the circuit is simulated at 32 nm process technology by using HSPICE simulation at supply voltage of 0.9 V in MOS, short gate (SG) and low power (LP) mode at 10 MHz frequency. Comparison is done on the basis of power dissipation, propagation delay and unity noise gain. FinFET technology in SG mode reduces propagation delay while LP mode reduces power dissipation. Maximum power saved by ultra low power stacked (ULP-ST) domino logic for 8 and 16 input OR at 15.5, 18.39% in SFLD, 32.91, 28.22% in HSD, 40.60, 44.67% in CKD in SG mode and for LP mode 18.26, 21.68% in SFLD, 28.84, 27.94% in HSD, 55.45, 44.59% in CKD, respectively.