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Tim Tri Hoang

Altera

6

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A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links

2014 EMC | International Symposium on Electromagnetic Compatibility
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Using VFTLP data to design for CDM robustness

2009 Electrical Overstress/Electrostatic Discharge Symposium
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A Reset Control Apparatus for PLL Power-Up Sequence and Auto-Synchronization

2008
- Kazi Asaduzzaman
- Tim Tri Hoang
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Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment

2003 CICC | Custom Integrated Circuits Conference
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