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Hideyuki Nakamura
Hideyuki Nakamura
Renesas Electronics
Electronic engineering
Physics
Soft error
Neutron
Logic gate
6
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75
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Scaling effect and circuit type dependence of neutron induced single event transient
2012
IRPS | International Reliability Physics Symposium
Hideyuki Nakamura
Taiki Uemura
Kan Takeuchi
Toshikazu Fukuda
Shigetaka Kumashiro
Tohru Mogami
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Measurement of neutron-induced single event transient pulse width narrower than 100ps
2010
IRPS | International Reliability Physics Symposium
Hideyuki Nakamura
Katsuhiko Tanaka
Taiki Uemura
Kan Takeuchi
Toshikazu Fukuda
Shigetaka Kumashiro
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Synthetic soft error rate simulation considering neutron-induced single event transient from transistor to LSI-chip level
2008
SISPAD | International Conference on Simulation of Semiconductor Processes and Devices
M. Hane
Hideyuki Nakamura
Katsuhiko Tanaka
Kentaro Watanabe
Yoshiharu Tosaka
Kiyoshi Ishikawa
Shigetaka Kumashiro
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Citations (9)
Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation
2004
IEDM | International Electron Devices Meeting
Yukiya Kawakami
M. Hane
Hideyuki Nakamura
T. Yamada
K. Kumagai
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Citations (30)
A new comprehensive SRAM soft-effor simulation based on 3D device simulation incorporating neutron nuclear reactions
2003
SISPAD | International Conference on Simulation of Semiconductor Processes and Devices
M. Hane
Yukiya Kawakami
Hideyuki Nakamura
Takashi Yamada
Kouich Kumagai
Yukinobu Watanabe
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Citations (4)
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