Synthetic soft error rate simulation considering neutron-induced single event transient from transistor to LSI-chip level

Soft error phenomena induced by the Sea-level cosmic neutron have been investigated by using a simulation system that covers from an individual MOSFET device level to an LSI-chip level. This system consists of the several kinds of simulation codes/tools, such as a mixed-mode 3D device simulator, SPICE circuit simulator, and analyzing tools of gate-level net-lists. A comprehensive practical simulation flow is demonstrated in this paper on commercial 90 nm generation logic devices and standard-cells.